PIC16C711-04/P【PDF 175/177 页】IC MCU OTP 1KX14 A/D 18DIP

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7593L–AVR–09/12

AT90USB64/128

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (f

ExtClk < fclk_I/O/2) given a 50/50% duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, due to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximum frequency of an external clock source is less than f

clk_I/O/2.5.

An external clock source can not be prescaled.

Figure 13-2. Prescaler for synchronous Timer/Counters

13.4

GTCCR – General Timer/Counter Control Register

Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond-

ing prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are

halted and can be configured to the same value without the risk of one of them advancing during

configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared

by hardware, and the Timer/Counters start counting simultaneously.

Bit 0 – PSRSYNC: Prescaler Reset for Synchronous Timer/Counters

When this bit is one, Timer/Counter0 and Timer/Counter1 and Timer/Counter3 prescaler will be

Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note

that Timer/Counter0, Timer/Counter1 and Timer/Counter3 share the same prescaler and a reset

of this prescaler will affect all timers.

PSR10

Clear

clk

I/O

Synchronization

TIMER/COUNTERn CLOCK SOURCE

clk

TIMER/COUNTERn CLOCK SOURCE

clk

CSn0

CSn1

CSn2

CSn0

CSn1

CSn2

Bit

TSM

–

PSRASY

PSRSYNC

GTCCR

Read/write

R/W

Initial value

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